The invention relates to a data control circuit which is described more particularly as a control circuit for a highly flexible serial input/output arrangement of a data procesor.
In the prior art, there is a telegraph type signal subchannel that utilizes control signals and decoding logic to select a baud rate, a word length, synchronous/asynchronous mode of operation, and a specific number of stop bits in each binary word transmitted serially between the subchannel and a terminal device. These control signals may be supplied by a communications controller under the control of a program from the data processor. Since the control signals are supplied by the data processor, they can be changed when it is desirable to change the baud rate, the word length, the mode of operation, or the number of stop bits.
To assure synchronization of the receiver, start and stop bits are included in the serial transmission of every data word. A problem of poor time efficiency arises for this arrangement because all transmitted words include start and stop bits which are transmitted in serial with the data word being transmitted. These start and stop bits reduce the time efficiency of transmission. Time efficiency for serial transmission of start and stop pulses is represented by an expression ##EQU1## where n equals the number of data bits per word, and the start and stop bits each has the same pulse width as every data bit.
The problem of poor time efficiency can be solved by transmitting clock and synchronization pulses in parallel channels separate from the channel carrying the data characters. This eliminates the time otherwise required for transmitting the start and stop bits during the transmission of every word. Time efficiency is improved because only the time for transmitting the basic data word is used. Time efficiency for parallel transmission of the start and stop pulses is 100 percent because no data transmission time is used for transmitting either start or stop bits.